1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a self-refresh mode.
2. Description of the Background Art
Conventionally, a dynamic random access memory (hereinafter referred to as DRAM) is provided with an address generating circuit that, in response to an instruction for execution of self-refresh, sequentially generates a plurality of address signals one by one, which are pre-allocated to a plurality of memory cell rows respectively, with a predetermined cycle, and designates memory cell rows to be refreshed by the generated address signals.
FIG. 11 is a block diagram showing the configuration of such an address generating circuit 150. Referring to FIG. 11, address generating circuit 150 includes a constant current circuit 151, a voltage converting circuit 152, a voltage control oscillation circuit 153, a count control signal generating circuit 154, a trimming switching circuit 155, five counting circuits 156 to 160, a detection circuit 161, and an address counter 162.
Constant current circuit 151 generates constant current of a predetermined value, and outputs a constant voltage VBN of a value corresponding to the constant current. Voltage converting circuit 152 is activated in response to a self-refresh instruction signal SR being set to an activated level of a logic high or xe2x80x9cHxe2x80x9d level, and converts output voltage VBN of constant current circuit 151 into a constant voltage VB of a predetermined value. Voltage control oscillation circuit 153 is activated in response to self-refresh instruction signal SR being set to the activated level of xe2x80x9cHxe2x80x9d level, and generates a clock signal CLK having a cycle obtained by dividing a refresh cycle by an integer, in accordance with output voltage VB of voltage converting circuit 152.
Count control signal generating circuit 154 includes, as shown in FIG. 12, inverters 163 to 165, a delay circuit 166, an NAND gate 167 and an NOR gate 168. Clock signal CLK generated at voltage control oscillation circuit 153 is input into one input node of each of NAND gate 167 and NOR gate 168 via inverter 163, delay circuit 166 and inverter 164, and is also input into the other input node of each of NAND gate 167 and NOR gate 168. As shown in FIG. 13, delay circuit 166 includes an even number (six in FIG. 13) of inverters 171 to 176 connected in series. An output clock signal of NAND gate 167 is inverted at inverter 165 to be a count clock signal CK1. An output clock signal of NOR gate 168 is a determination clock signal CK2. Each of clock signals CK1 and CK2 has the same cycle as that of clock signal CLK, and both clock signals CK1 and CK2 are non-overlapped two-phase clock signals that are not set to the xe2x80x9cHxe2x80x9d level at a time.
Referring again to FIG. 11, trimming switching circuit 155 includes five fuses, and is activated by output voltage VBN of constant current circuit 151, setting each of signals xcfx860 to xcfx864 to be at the xe2x80x9cHxe2x80x9d level or an xe2x80x9cL (logic low)xe2x80x9d level, depending on the state of each of the five fuses (i.e. whether or not each fuse blown). Signals xcfx860 to xcfx864 are applied to counting circuits 156 to 160 respectively.
Referring to FIG. 14, counting circuit 156 includes inverters 180 to 186, transfer gates 187 to 189, and clocked inverters 190, 191. Inverters 182, 183, 190 and 191, and transfer gates 188, 189 constitute a flip-flop 192. Flip-flop 192 captures a level of an input terminal 192a when count clock signal CK1 is at the xe2x80x9cLxe2x80x9d level, and outputs a signal of the captured level in response to count clock signal CK1 being raised from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level. Inverter 184 is connected between an output terminal 192b and input terminal 192a of flip-flop 192. An output signal of inverter 180 is inverted at inverter 186 to be an output clock signal CY0 of counting circuit 156. Therefore, clock signal CY0 is a signal obtained by frequency-dividing clock signal CK1 by two.
Inverters 180, 181 and transfer gate 187 constitute a preset circuit. Transfer gate 187 is rendered conductive while preset signal PR is at an activated level of xe2x80x9cHxe2x80x9d level, and a signal xcfx860 is applied to a latch circuit constituted by inverters 183, 191 via inverter 180 and transfer gate 187. This makes signal xcfx860 and output clock signal CY0 be at the same logic level.
Counting circuit 157 is formed, as shown in FIG. 15, by removing inverter 181 from counting circuit 156 and adding NAND gates 193, 194, inverters 195, 196 and a transfer gate 197 thereto. Moreover, flip-flop 192 operates in synchronization with output clock signal CY0 of counting circuit 156, in place of count clock signal CK1. Thus, output clock signal CY1 of counting circuit 157 is a signal obtained by frequency-dividing output clock signal CY0 of counting circuit 156 in the previous stage by two.
Inverters 180, 195, 196, transfer gates 187, 197, and NAND gates 193, 194 constitute a preset circuit. When preset signal PR is set to the xe2x80x9cHxe2x80x9d level while clock signal CY0 is at the xe2x80x9cHxe2x80x9d level, transfer gate 197 is rendered conductive, and a signal xcfx861 is applied to a latch circuit constituted by inverters 182 and 190 via transfer gate 197. When preset signal PR is set to the xe2x80x9cHxe2x80x9d level while clock signal CY0 is at the xe2x80x9cLxe2x80x9d level, transfer gate 187 is rendered conductive, and signal xcfx861 is applied to a latch circuit constituted by inverters 183 and 191 via inverter 180 and transfer gate 187. In either case, signal xcfx861 and output clock signal CY1 have the same logic level.
Counting circuits 158 to 160 have the same configuration as that of counting circuit 157. Counting circuit 158 outputs a clock signal CY2 obtained by frequency-dividing output clock signal CY1 of counting circuit 157 by two. Counting circuit 159 outputs a clock signal CY3 obtained by frequency-dividing output clock signal CY2 of counting circuit 158 by two. Counting circuit 160 outputs a clock signal CY4 obtained by frequency-dividing output clock signal CY3 of counting circuit 159 by two. Thus, output clock signals CY0 to CY4 of counting circuits 156 to 160 have frequencies twice, four times, eight times, sixteen times and thirty-two times, respectively, as much as the frequency of clock signal CK1. Moreover, the timing of rising edges of clock signals CY0 to CY4 can be changed by trimming switching circuit 155.
As shown in FIG. 16, detection circuit 161 includes NAND gates 201 to 207, an NOR gate 208 and an inverter 209, in which NAND gates 205 and 206 constitute a flip-flop 210. NAND gate 201 receives clock signals CY0 to CY2, NAND gate 202 receives clock signals CY3 and CY4, and NOR gate 208 receives output signals of NAND gates 201 and 202. NAND gate 203 receives a determination clock signal CK2 and a self-refresh instruction signal SR, and the output signal thereof is input into a reset terminal 210b of flip-flop 210 via inverter 209. NAND gate 204 receives an output signal xcfx86208 of NOR gate 208 and an output signal of inverter 209, and an output signal of NAND gate 204 is input into a set terminal 210a of flip-flop 210. An output signal of flip-flop 210 is a signal PHYS indicating a refresh cycle. NAND gate 207 receives an inversion output signal of flip-flop 210 and self-refresh instruction signal SR, and outputs a preset signal PR.
When self-refresh instruction signal SR is at the xe2x80x9cLxe2x80x9d level, the output signal of inverter 209 is fixed at the xe2x80x9cLxe2x80x9d level, resetting flip-flop 210, and thus signal PHYS is set to the xe2x80x9cLxe2x80x9d level, whereas preset signal PR is set to the xe2x80x9cHxe2x80x9d level. When self-refresh instruction signal SR is at the xe2x80x9cHxe2x80x9d level, each of NAND gates 203 and 207 operates as an inverter. When at least one of clock signals CY0 to CY4 is at the xe2x80x9cLxe2x80x9d level, output signal xcfx86208 of NOR gate 208 is lowered to the xe2x80x9cLxe2x80x9d level and set terminal 210a of flip-flop 210 is raised to the xe2x80x9cHxe2x80x9d level, while determination clock signal CK2 is input into reset terminal 210b of flip-flop 210 via NAND gate 203 and inverter 209. This resets flip-flop 210, making both of signal PHYS and preset signal PR be at the xe2x80x9cLxe2x80x9d level.
When all of clock signals CY0 to CY4 are set to the xe2x80x9cHxe2x80x9d level, output signal xcfx86208 of NOR gate 208 is raised to the xe2x80x9cHxe2x80x9d level, and NAND gate 204 operates as an inverter. Thus, flip-flop 210 is set in response to a rising edge of clock signal CK2, and is reset in response to a falling edge of clock signal CK2. Clock signal CY0 has a cycle twice as long as that of clock signal CK2, so that flip-flop 210 is set only once. When flip-flop 210 is set, both of signal PHYS and preset signal PR are set to the xe2x80x9cHxe2x80x9d level, whereas when flip-flop 210 is reset, both of signal PHYS and preset signal PR are lowered to the xe2x80x9cLxe2x80x9d level. Therefore, counting circuits 156 to 160 and detection circuit 161 constitute a 5-bit subtraction counting circuit. An initial value of the subtraction counting circuit is set by trimming switching circuit 155, and subtraction is performed in synchronization with count clock signal CK1.
Referring again to FIG. 11, address counter 162 is activated by self-refresh instruction signal SR, and counts the number of pulses of output clock signal PHYS in detection circuit 161 to output address signals A0 to A11. Therefore, address signals A0 to A11 are incremented with the same cycle as that of clock signal PHYS. Every time one of address signals A0 to A11 is output, data in one memory cell row is refreshed. When address counter 162 counts up, refresh of data is terminated for all the memory cell rows.
However, conventional address generating circuit 150 generates reference clock signal CLK by voltage control oscillation circuit 153, and generates five clock signals CY0 to CY4 by sequentially frequency-dividing clock signal CLK at counting circuits 156 to 160, to obtain a refresh cycle based on such clock signals CY0 to CY4. This has disadvantageously increased power consumption and circuit scale of voltage control oscillation circuit 153 and counting circuits 156 to 160.
Therefore, a principle object of the present invention is to provide a semiconductor memory device having small power consumption and circuit scale.
According to one aspect of the present invention, a semiconductor memory device includes a voltage control oscillation circuit generating a clock signal with a cycle according to a control voltage; a refresh execution circuit activated during a self-refresh mode, to sequentially select a plurality of memory cell rows in synchronization with the clock signal and to refresh data in selected memory cell rows; a signal generating circuit including at least one fuse, and outputting a signal for setting a cycle of the clock signal based on whether or not the fuse is blown; and a voltage generating circuit generating a control voltage for the voltage control oscillation circuit in accordance with an output signal of the signal generating circuit. Thus, self refresh is performed in synchronization with the output clock signal of the voltage control oscillation circuit, allowing smaller power consumption and circuit scale, compared to the conventional case in which a plurality of clock signals were generated by frequency-dividing a reference clock signal, generated at the voltage control oscillation circuit, by a plurality of counting circuits, to perform self-refresh based on the generated plurality of clock signals.
Preferably, the voltage generating circuit includes a constant current circuit supplying constant current of a predetermined value to an output node for outputting the control voltage; a plurality of diode elements; and a switching circuit selecting any one or more of the plurality of diode elements in accordance with an output signal of the signal generating circuit, and connecting each selected diode element between the output node and a line of a reference potential. Thus, by changing the number of diode elements connected between the output node and the line of the reference potential, the control voltage can be changed.
More preferably, the diode element includes a transistor whose input electrode and one conduction electrode are connected, and a plurality of transistors included in the plurality of diode elements have different sizes. Thus, multiple stages of control voltages can be generated by a small number of diode elements.
More preferably, the sizes of the plurality of transistors are sequentially doubled. This can generate a control voltage obtained by multiplying a control voltage to be a reference by a desired integer.
More preferably, the switching circuit of the voltage generating circuit includes a plurality of switching elements provided to correspond to the plurality of diode elements respectively, each of which is connected in series with a corresponding diode element, between said output node and the line of said reference potential. The fuse of the signal generating circuit is provided in a number equal to the number of the switching elements, to correspond to each switching element. The signal generating circuit further includes a driving circuit provided corresponding to each fuse, to render a corresponding switching element conductive or non-conductive in response to a corresponding fuse being blown. Thus, the switching circuit and signal generating circuit can easily be configured.
More preferably, the signal generating circuit further includes a selection circuit selecting whether the driving circuit renders a corresponding switching element conductive or non-conductive, in response to a corresponding fuse being blown. Thus, the number of fuses to be blown can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.